1. Field of the Invention
The present invention generally relates to a semiconductor memory device and a method of fabricating the same and, more particularly, to a semiconductor memory device that is microscopic in size and long in storage retention time and especially suitable for a dynamic random access memory (hereafter referred to as DRAM) and a method of fabricating such a semiconductor memory device.
2. Description of the Prior Art
The DRAM has been increasing in integration density at a rate as high as four times every three years. Currently, DRAMs of which integration densities are 16 megabits and 64 megabits are mass-produced and mass-production of gigabit-order DRAMs is being planned. Such high integration has been achieved miniaturizing the planar and depth dimensions of the DRAM. However, the miniaturization lowers the signal-to-noise ratio because of the reduction in the amount of charge that can be built up and makes conspicuous troubles such as signal reversal due to the incidence of alpha ray, presenting a serious problem of reliability maintenance.
Consequently, a memory cell that can increase storage capacity has been strongly desired. For such a memory cell, Japanese Published Unexamined Patent Application No. Sho 53-108392 (Japanese Published Examined Patent Application No. Sho 61-55528) discloses a structure as shown in FIG. 15. The memory cell having the disclosed structure is called a stacked capacitor cell (STC) in which a part of a storage capacitor is stacked on a switch transistor or an isolation insulating transistor. This memory cell is expected to replace the conventional planar capacitor cell.
Referring to FIG. 15, reference numeral 2.1 denotes a semiconductor substrate, reference numeral 2.2 an isolation insulating film, reference numeral 2.3 a channel portion of a switching transistor, reference numerals 2.4 and 2.5 impurity diffused layers, reference numeral 2.6 a gate insulating film, reference numeral 2.7 a word line providing the gate electrode of switching transistor, reference numeral 2.9 a bit line, reference numerals 2.10 and 2.14 interlayer insulating films, reference numeral 2.11 a lower electrode of storage capacitor, reference numeral 2.12 a dielectric film of storage capacitor, reference numeral 2.13 a plate electrode (upper electrode) of storage capacitor, and reference numeral 2.15 a wiring metal. The bit line 2.9 is electrically connected to the impurity diffused layer 2.4 through an extended electrode 2.8. The lower electrode 2.11 is electrically connected to the impurity diffused layer 2.5.
With the conventional STC cell shown in FIG. 15, the lower electrode 2.11 of the storage capacitor can be extended over the word line 2.7, so that far greater storage capacitance can be realized than that of the planar capacitor cell that uses only the surface of semiconductor substrate as a storage capacitor.
The STC cell shown in FIG. 15 is fabricated through the following processes. First, a relatively thick (about 100 to 1000 nm) silicon oxide film for electrically separating elements is grown on the semiconductor substrate 2.1 made of single-crystal silicon by known thermal oxidation to form the isolation insulating film. The gate electrode of transistor 2.6 (about 5 to 50 nm) is grown by known thermal oxidation. Then, an impurity-doped polycrystalline silicon film is formed, which is worked into a predetermined shape by known photo-lithography and dry-etching to form the word line 2.7. Using the word line 2.7 as a mask, an impurity having a different conductive type from that of the semiconductor substrate 2.1 is introduced into the same by a known ion implantation technique. Then, predetermine thermal processing is performed to activate the above-mentioned doped impurity to form the impurity-diffused layers 2.4 and 2.5.
Next, a polycrystalline silicon film of the same conductive type is formed by known CVC (Chemical Vapor Deposition) such that the film comes in contact with the above-mentioned impurity-diffused layer 2.5. The unwanted portions of the film thus formed are removed by etching to form the lower electrode 2.11 of the storage capacitor. As is clear from FIG. 15, the above-mentioned lower electrode 2.11 is formed also extending over the word line 2.7 and the isolation insulating film 2.2, so that the area of the lower electrode 2.11 of the storage capacitor becomes extremely large, resulting in an increased amount of charge to be stored.